Partial reconfiguration (PR) is a key enabler to the design and development of adaptive systems on modern Field Programmable Gate Array (FPGA) Systems-on-Chip (SoCs), allowing hardware to be adapted dynamically at runtime. Vendor supported PR infrastructure is performance limited and blocking, drivers entail complex memory management, and software/hardware design requires bespoke knowledge of the underlying hardware. This paper presents ZyPR: a complete end-to-end framework that provides high performance reconfiguration of hardware from within a software abstraction in the Linux userspace, automating the process of building PR applications, with support for the Xilinx Zynq and Zynq UltraScale+ architectures, aimed at enabling non-expert application designers to leverage PR for edge applications. We compare ZyPR against traditional vendor tooling for PR management as well as recent open source tools that support PR under Linux. The framework provides a high performance runtime along with low overhead for its provided abstractions. We introduce improvements to our previous work, increasing the provisioning throughput for PR bitstreams on the Zynq Ultrascale+ by 2 × and 5.4 × compared to Xilinx’s FPGA Manager.
|Original language||English (US)|
|Journal||ACM Transactions on Reconfigurable Technology and Systems|
|State||Published - Feb 27 2023|
Bibliographical noteKAUST Repository Item: Exported on 2023-03-02
Acknowledgements: This work was supported by the UK Engineering and Physical Sciences Research Council, grant EP/N509796/1.
ASJC Scopus subject areas
- Computer Science(all)