Work-in-progress: Eficient pulsed-latch implementation for multiport register files

Wael M. Elsharkasy, Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


In this paper, register file design using pulsed latches is presented. Having some advantages in performance, area and power, pulsed latches represent an attractive implementation of register files. In addition, a proposed multiport register file architecture is introduced using single physical read/write ports to virtualize additional ports for read and write. The initial results show huge savings in area and power in comparison to the traditional architectures.
Original languageEnglish (US)
Title of host publicationProceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017
PublisherAssociation for Computing Machinery,
ISBN (Print)9781450351843
StatePublished - Oct 15 2017
Externally publishedYes

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