VLSI Architecture Design of 9/7 Discrete Wavelet Transform for Image Processing

Sadaf Javed, Ch Jabbar Younis, Mehboob Alam, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations


In image processing, transform coding de-correlates images to pre-condition them for efficient compression. In this work, we propose VLSI architecture design of a hardware-efficient 9/7 Discrete Wavelet Transform (DWT). The architecture takes advantage of Canonical Signed Digit (CSD) and Distributed Arithmetic (DA) to represent and optimally distribute co-efficients to reduce the number of adder and shift registers. In addition, the co-efficient multiplication also exploits the horizontal and vertical redundancy in the architecture to reduce the hardware computational complexity. The result is a filter-based design, exploiting hardware path of architecture using CSD coefficients, which finds minimum realization. The proposed architecture is simulated using Verilog Hardware Description Language (HDL). A comparison with other architectures of 9/7 DWT shows a 18.75% reduction in hardware. The result is a hardware-efficient architecture, which provides a low-power solution for image and signal processing applications.
Original languageEnglish (US)
Title of host publicationMidwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)9781728127880
StatePublished - Aug 1 2019
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2022-09-13


Dive into the research topics of 'VLSI Architecture Design of 9/7 Discrete Wavelet Transform for Image Processing'. Together they form a unique fingerprint.

Cite this