VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform

Raja Arslan Naseer, Muneeba Nasim, Muhummad Sohaib, Ch Jabbar Younis, Anzar Mehmood, Mehboob Alam, Yehia Mahmoud Massoud

Research output: Contribution to journalArticlepeer-review


Discrete Wavelet Transform (DWT) is considered among the few computationally expensive block of multimedia compression standards. In this work, we proposed a reduced hardware complexity VLSI architectures of 5/3 and 9/7 lifting bi-orthogonal DWT for multimedia applications. The architecture uses a combination of Distribute Arithmetic (DA) and Canonical Signed Digit (CSD) based implementation to reduce the hardware complexity. The resulting lifting based architecture discretely finds optimized number of sum of products to give minimum realization. The architecture is implemented on Field Programmable Gate Array (FPGA) with results compared with known classical and other optimized DWT architectures.
Original languageEnglish (US)
Pages (from-to)253-259
Number of pages7
StatePublished - Aug 18 2022

Bibliographical note

KAUST Repository Item: Exported on 2022-09-09
Acknowledgements: The authors extend their appreciation to the Mirpur University of Science and Technology (MUST), University of Poonch Rawalakot and Innovative Technologies Laboratories (ITL), King Abdullah University of Science and Technology for supporting this research.

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering


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