Vertically Stacked Nanosheet FET: Charge- Trapping Memory and Synapse With Linear Weight Adjustability for Neuromorphic Computing Applications

Md Hasan Raza Ansari, Hanrui Li, Nazek El-Atab*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

This work shows the feasibility of a vertically stacked nanosheet field effect transistor (NSFET) for charge-trapping memory and artificial synaptic devices. The artificial synapse's behaviors, long-term potentiation (LTP), and long-term depression (LTD) are analogous to erase (ERS) and program (PGM) of charge-trapping memory, respectively. This NSFET device with a gate length of 50 nm achieves a wider memory window (MW), long retention time for programming, and infinite retention (> 108 s) for ERS operation. The results also show linear synaptic features with nonlinearity values of 2.50 and -0.42 for LTP and LTD, respectively. Furthermore, the device conductance values are utilized as synaptic weights for image recognition of Modified National Institute of Standards and Technology (MNIST) dataset in neural networks and achieve 93.30% accuracy. These results make it a promising candidate for next-generation charge-trapping memory and neuromorphic computing due to its wide memory window, long retention, high accuracy, and high density.

Original languageEnglish (US)
Pages (from-to)1344-1350
Number of pages7
JournalIEEE TRANSACTIONS ON ELECTRON DEVICES
Volume70
Issue number3
DOIs
StatePublished - Mar 1 2023

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

  • Depression
  • long-term depression (LTD)
  • long-term potentiation (LTP)
  • nanosheet field effect transistor (NSFET)
  • neural network
  • neuromorphic computing
  • potentiation
  • synaptic transistor

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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