Abstract
The quantization of weights to binary states in Deep Neural Networks (DNNs) can replace resource-hungry multiply accumulate operations with simple accumulations. Such Binarized Neural Networks (BNNs) exhibit greatly reduced resource and power requirements. In addition, memristors have been shown as promising synaptic weight elements in DNNs. In this paper, we propose and simulate novel Binarized Memristive Convolutional Neural Network (BMCNN) architectures employing hybrid weight and parameter representations. We train the proposed architectures offline and then map the trained parameters to our binarized memristive devices for inference. To take into account the variations in memristive devices, and to study their effect on the performance, we introduce variations in RON and ROFF. Moreover, we introduce means to mitigate the adverse effect of memristive variations in our proposed networks. Finally, we benchmark our BMCNNs and variation-aware BMCNNs using the MNIST dataset.
Original language | English (US) |
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Title of host publication | 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 490-493 |
Number of pages | 4 |
ISBN (Electronic) | 9781728109961 |
DOIs | |
State | Published - Nov 2019 |
Event | 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 - Genoa, Italy Duration: Nov 27 2019 → Nov 29 2019 |
Publication series
Name | 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 |
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Conference
Conference | 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 |
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Country/Territory | Italy |
City | Genoa |
Period | 11/27/19 → 11/29/19 |
Bibliographical note
Publisher Copyright:© 2019 IEEE.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Control and Optimization
- Computer Networks and Communications
- Hardware and Architecture