Using reconfigurable multi-core architectures for safety-critical embedded systems

Tom Guillaumet, Aayush Sharma, Eric Feron, Madhava Krishna, Ranjani Narayan, Philippe Baufreton, Francois Neumann, Emmanuel Grolleau

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


With the onset of multi- and many-core chips, the single-core market is closing down. Those chips constitute a new challenge for aerospace and safety-critical industries in general. Little is known about the certification of software running on these systems. There is therefore a strong need for developing software architectures based on multi-core architectures, yet compliant with safety-criticality constraints. This paper presents a reconfigurable multi-core architecture and the safety-criticality constraints for airborne systems. The last section uses the current certification guidance to explain how the architecture can satisfy these constraints even with dynamic features activated.
Original languageEnglish (US)
Title of host publicationAIAA/IEEE Digital Avionics Systems Conference - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781509056002
StatePublished - Dec 7 2016
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2021-02-18


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