TRAM: A tool for temperature and reliability aware memory design

Amin Khajeh; Aseem Gupta; Nikil Dutt; Fadi Kurdahi; Ahmed Eltawil; Kamal Khouri; Magdy Abadir

TRAM: A tool for temperature and reliability aware memory design

Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi Kurdahi, Ahmed Eltawil, Kamal Khouri, Magdy Abadir

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vdd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors. © 2009 EDAA.

Original language	English (US)
Title of host publication	Proceedings -Design, Automation and Test in Europe, DATE
State	Published - Oct 22 2009
Externally published	Yes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2019-11-20

Cite this

@inproceedings{3e70e1c1e05e48c88ac25d5fc9d8ae32,

title = "TRAM: A tool for temperature and reliability aware memory design",

abstract = "Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vdd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors. {\textcopyright} 2009 EDAA.",

author = "Amin Khajeh and Aseem Gupta and Nikil Dutt and Fadi Kurdahi and Ahmed Eltawil and Kamal Khouri and Magdy Abadir",

note = "Generated from Scopus record by KAUST IRTS on 2019-11-20",

year = "2009",

month = oct,

day = "22",

language = "English (US)",

isbn = "9783981080155",

booktitle = "Proceedings -Design, Automation and Test in Europe, DATE",

}

TY - GEN

T1 - TRAM: A tool for temperature and reliability aware memory design

AU - Khajeh, Amin

AU - Gupta, Aseem

AU - Dutt, Nikil

AU - Kurdahi, Fadi

AU - Eltawil, Ahmed

AU - Khouri, Kamal

AU - Abadir, Magdy

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20

PY - 2009/10/22

Y1 - 2009/10/22

N2 - Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vdd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors. © 2009 EDAA.

AB - Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vdd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors. © 2009 EDAA.

UR - http://www.scopus.com/inward/record.url?scp=70350043910&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9783981080155

BT - Proceedings -Design, Automation and Test in Europe, DATE

ER -

TRAM: A tool for temperature and reliability aware memory design

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