Abstract
Programmable hardware accelerators (e.g., vector processors, GPUs) have been extremely successful at targeting algorithms with regular control and memory patterns to achieve order-of-magnitude performance and energy efficiency improvements. However, they perform far under the peak on important irregular algorithms, like those from graph processing, database querying, genomics, advanced machine learning, and others. This work posits that the primary culprit is specific forms of irregular control flow and memory access. By capturing the problematic behavior at a domain-agnostic level, we propose an accelerator that is sufficiently general, matches domain-specific accelerator performance, and significantly outperforms traditional CPUs and GPUs.
Original language | English (US) |
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Article number | 9069252 |
Pages (from-to) | 37-46 |
Number of pages | 10 |
Journal | IEEE Micro |
Volume | 40 |
Issue number | 3 |
DOIs | |
State | Published - May 1 2020 |
Bibliographical note
Publisher Copyright:© 1981-2012 IEEE.
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering