In this paper, we investigate the timing implications of dummy fill for large-scale designs implemented in 65 nm process technology. For each design, we employ each of rule-based and model-based metal fill generation techniques and model the incremental path-wise delay increases and the level of interconnect planarization due to the fill metal. The results indicate that fill metal can cause significant increases in the average delay and in the individual path delays. We also find that model-based fill generation methods can provide significantly better incremental delay increases and interconnect planarization than rule-based methods. This study provides the first comprehensive investigation of the delay and interconnect planarization implications of rule-based as well as model-based fill generation for large-scale designs implemented in nano-scale process technology. ©2008 IEEE.
|Original language||English (US)|
|Title of host publication||Midwest Symposium on Circuits and Systems|
|Number of pages||4|
|State||Published - Oct 27 2008|