Timing implications of fill metal generation methods for system-level nano-scale designs

Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


In this paper, we investigate the timing implications of dummy fill for large-scale designs implemented in 65 nm process technology. For each design, we employ each of rule-based and model-based metal fill generation techniques and model the incremental path-wise delay increases and the level of interconnect planarization due to the fill metal. The results indicate that fill metal can cause significant increases in the average delay and in the individual path delays. We also find that model-based fill generation methods can provide significantly better incremental delay increases and interconnect planarization than rule-based methods. This study provides the first comprehensive investigation of the delay and interconnect planarization implications of rule-based as well as model-based fill generation for large-scale designs implemented in nano-scale process technology. ©2008 IEEE.
Original languageEnglish (US)
Title of host publicationMidwest Symposium on Circuits and Systems
Number of pages4
StatePublished - Oct 27 2008
Externally publishedYes

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Generated from Scopus record by KAUST IRTS on 2022-09-13


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