Thermally robust clocking schemes for 3D integrated circuits

Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg Link, N. Vijaykrishnan, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Scopus citations


3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers. However, dissipating the heat generated in the 3D chips possesses a major challenge to the success of the technology and is the subject of active current research. Since the generated heat degrades the performance of the chip, thermally insensitive/adaptive circuit design techniques are required for better overall system performance. In this paper, we propose a thermally adaptive 3D clocking scheme that dynamically adjusts the driving strengths of the clock buffers to reduce the clock skew between terminals. We investigate the relative merits and demerits of two alternative clock tree topologies in this work. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by 61.65% on the average, leading to much improved clock synchronization and design performance in the 3D realm. © 2007 EDAA.
Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Number of pages6
StatePublished - Sep 4 2007
Externally publishedYes

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