The Path to Fault- and Intrusion-Resilient Manycore Systems on a Chip

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The hardware computing landscape is changing. What used to be distributed systems can now be found on a chip with highly configurable, diverse, specialized and general purpose units. Such Systems-on-a-Chip (SoC) are used to control today’s cyber-physical systems, being the building blocks of critical infrastructures. They are deployed in harsh environments and are connected to the cyberspace, which makes them exposed to both accidental faults and targeted cyberattacks. This is in addition to the changing fault landscape that continued technology scaling, emerging devices and novel application scenarios will bring. In this paper, we discuss how the very features—distributed, parallelized, reconfigurable, heterogeneous—that cause many of the imminent and emerging security and resilience challenges, also open avenues for their cure though SoC replication, diversity, rejuvenation, adaptation, and hybridization. We show how to leverage these techniques at different levels across the entire SoC hardware/software stack, calling for more research on the topic.
Original languageEnglish (US)
Title of host publication2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)
StatePublished - Aug 10 2023

Bibliographical note

KAUST Repository Item: Exported on 2023-08-14


Dive into the research topics of 'The Path to Fault- and Intrusion-Resilient Manycore Systems on a Chip'. Together they form a unique fingerprint.

Cite this