Task allocation of safety-critical applications on reconfigurable multi-core architectures

Tom Guillaumet, Eric Feron, Philippe Baufreton, François Neumann, Kavitha Madhu, Madhava Krishna, S. K. Nandy, Ranjani Narayan, Chandan Haldar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


With the onset of multi-core chips, the single-core market is closing down. Developing avionics systems hosted on multi-core chips that enforce safety-criticality constraints constitutes a challenge for the aerospace industry. This paper presents a reconfigurable multi-core architecture and studies its suitability for hosting safety-critical embedded applications. A task allocation algorithm for this specific architecture is proposed, and the last section demonstrates its behavior and analyzes its efficiency.
Original languageEnglish (US)
Title of host publicationAIAA/IEEE Digital Avionics Systems Conference - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781538603659
StatePublished - Nov 8 2017
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2021-02-18


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