Tardis : A Fault-Tolerant Design for Network Control Planes

Zhenyu Zhou, Theophilus A. Benson, Marco Canini, Balakrishnan Chandrasekaran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Guaranteeing high availability of networks virtually hinges on the ability to handle and recover from bugs and failures. Yet, despite the advances in verification, testing, and debugging, production networks remain susceptible to large-scale failures - - often due to deterministic bugs. This paper explores the use of input transformations as a viable method for recovering from such deterministic bugs. In particular, we introduce an online system, Tardis, for overcoming deterministic faults by using a blend of program analysis and runtime program data to systematically determine the fault-triggering input events and using domain-specific models to automatically generate transformations of the fault-triggering inputs that are both safe and semantically equivalent. We evaluated Tardison several production network control plane applications (CPAs), including six SDN CPAs and several popular BGP CPAs using 71 realistic bugs. We observe that Tardisimproves recovery time by 7.44%, introduces a 25% CPU and 0.5% memory overhead, and recovers from 77.26% of the injected realistic and representative bugs, more than twice that of existing solutions.
Original languageEnglish (US)
Title of host publicationProceedings of the ACM SIGCOMM Symposium on SDN Research (SOSR)
PublisherACM
Pages108-121
Number of pages14
ISBN (Print)9781450390842
DOIs
StatePublished - Nov 8 2021

Bibliographical note

KAUST Repository Item: Exported on 2022-03-08
Acknowledgements: We thank the anonymous reviewers and our shepherd, Ryan Beckett, for their insightful comments. We also thank Ayush Bhardwaj for helping us with designing our experiments. This work was supported by NSF award CNS-1749785.

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