Abstract
A systematic study to optimize gate stack constituents (interface, high- κ, metal gate) to maximize carrier mobility with aggressively scaled equivalent oxide thickness (EOT) is presented. We identify ultra-thin thermal oxide, atomic layer deposited HfSiON and optimized plasma nitridation performed in sequence as the optimized run path for sub-nm EOT scaling with high carrier mobility. A metal gate deposition process that minimizes the incorporation of impurities in HfSiON is also vital to maintaining good mobility at low EOTs.
Original language | English (US) |
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Title of host publication | ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference |
Publisher | IEEE Computer Society |
Pages | 113-116 |
Number of pages | 4 |
ISBN (Print) | 1424403014, 9781424403011 |
DOIs | |
State | Published - 2006 |
Externally published | Yes |
Event | ESSDERC 2006 - 36th European Solid-State Device Research Conference - Montreux, Switzerland Duration: Sep 19 2006 → Sep 21 2006 |
Publication series
Name | ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference |
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Volume | 2006-January |
Other
Other | ESSDERC 2006 - 36th European Solid-State Device Research Conference |
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Country/Territory | Switzerland |
City | Montreux |
Period | 09/19/06 → 09/21/06 |
Bibliographical note
Publisher Copyright:©2006 IEEE.
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials