This paper addresses the fact that memory yield will be the dominant issue affecting overall yield in nano-seale devices. It illustrates that by treating yield as a system design parameter, tremendous gains in effective chip yield can be achieved. The techniques outlined are especially suited for applications that have inherent system redundancy such as wireless communication. In that context, the paper illustrates a that system redundancy can easily tolerate up to 1% bit errors in memory while meeting system specifications such as bit error rate (BER) metrics. ©2006 IEEE.
|Original language||English (US)|
|Title of host publication||2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers|
|State||Published - Oct 1 2007|