System-level SRAM yield enhancement

Fadi J. Kurdahi; Ahmed M. Eltawil; Young Hwan Park; Rouwaida N. Kanj; Sani R. Nassif

doi:10.1109/ISQED.2006.130

System-level SRAM yield enhancement

Fadi J. Kurdahi, Ahmed M. Eltawil, Young Hwan Park, Rouwaida N. Kanj, Sani R. Nassif

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

28 Scopus citations

Abstract

It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or SOC. Thus yield management of these SRAMs plays a crucial role in insuring design success. This paper demonstrates analysis techniques to model and improve the yield of SRAMs at the system level by proper accounting for the coupling between the algorithms targeted for an SOC and the performance, power, and yield of SRAMs used in implementing the algorithms. It is shown that coupling the algorithm and SRAM design phases provides significant advantages over independent optimization. © 2006 IEEE.

Original language	English (US)
Title of host publication	Proceedings - International Symposium on Quality Electronic Design, ISQED
DOIs	https://doi.org/10.1109/ISQED.2006.130
State	Published - Dec 1 2006
Externally published	Yes

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Generated from Scopus record by KAUST IRTS on 2019-11-20

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10.1109/ISQED.2006.130

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title = "System-level SRAM yield enhancement",

abstract = "It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or SOC. Thus yield management of these SRAMs plays a crucial role in insuring design success. This paper demonstrates analysis techniques to model and improve the yield of SRAMs at the system level by proper accounting for the coupling between the algorithms targeted for an SOC and the performance, power, and yield of SRAMs used in implementing the algorithms. It is shown that coupling the algorithm and SRAM design phases provides significant advantages over independent optimization. {\textcopyright} 2006 IEEE.",

author = "Kurdahi, {Fadi J.} and Eltawil, {Ahmed M.} and Park, {Young Hwan} and Kanj, {Rouwaida N.} and Nassif, {Sani R.}",

note = "Generated from Scopus record by KAUST IRTS on 2019-11-20",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/ISQED.2006.130",

language = "English (US)",

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AU - Kurdahi, Fadi J.

AU - Eltawil, Ahmed M.

AU - Park, Young Hwan

AU - Kanj, Rouwaida N.

AU - Nassif, Sani R.

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20

PY - 2006/12/1

Y1 - 2006/12/1

N2 - It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or SOC. Thus yield management of these SRAMs plays a crucial role in insuring design success. This paper demonstrates analysis techniques to model and improve the yield of SRAMs at the system level by proper accounting for the coupling between the algorithms targeted for an SOC and the performance, power, and yield of SRAMs used in implementing the algorithms. It is shown that coupling the algorithm and SRAM design phases provides significant advantages over independent optimization. © 2006 IEEE.

AB - It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or SOC. Thus yield management of these SRAMs plays a crucial role in insuring design success. This paper demonstrates analysis techniques to model and improve the yield of SRAMs at the system level by proper accounting for the coupling between the algorithms targeted for an SOC and the performance, power, and yield of SRAMs used in implementing the algorithms. It is shown that coupling the algorithm and SRAM design phases provides significant advantages over independent optimization. © 2006 IEEE.

UR - http://ieeexplore.ieee.org/document/1613133/

UR - http://www.scopus.com/inward/record.url?scp=84886733464&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2006.130

DO - 10.1109/ISQED.2006.130

M3 - Conference contribution

SN - 0769525237

BT - Proceedings - International Symposium on Quality Electronic Design, ISQED

ER -

System-level SRAM yield enhancement

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