TY - GEN
T1 - StrongARM Latch Comparator Performance Enhancement by Implementing Clocked Forward Body Biasing
AU - Alshehri, Abdullah
AU - Al-Qadasi, Mohammed
AU - Almansouri, Abdullah Saud Mohammed
AU - Al Attar, Talal
AU - Fariborzi, Hossein
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2019/1/24
Y1 - 2019/1/24
N2 - In this paper, we propose a forward body biasing technique to enhance the performance of the StrongARM comparators. We apply this technique, which is mainly based on clocked tuning of the threshold voltage of the NMOS cross-coupled transistors, to different architectures, namely: Kobayashi, Razavi, and Improved StrongARM comparators. The circuits are simulated in the standard 65nm CMOS technology and performance improvement of up to 20.8% has been achieved while maintaining the same energy loss.
AB - In this paper, we propose a forward body biasing technique to enhance the performance of the StrongARM comparators. We apply this technique, which is mainly based on clocked tuning of the threshold voltage of the NMOS cross-coupled transistors, to different architectures, namely: Kobayashi, Razavi, and Improved StrongARM comparators. The circuits are simulated in the standard 65nm CMOS technology and performance improvement of up to 20.8% has been achieved while maintaining the same energy loss.
UR - http://hdl.handle.net/10754/631288
UR - https://ieeexplore.ieee.org/document/8617903
UR - http://www.scopus.com/inward/record.url?scp=85062280351&partnerID=8YFLogxK
U2 - 10.1109/icecs.2018.8617903
DO - 10.1109/icecs.2018.8617903
M3 - Conference contribution
SN - 9781538695623
SP - 229
EP - 232
BT - 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -