Strain-enhanced scaling of HK+MG CMOSFETs

Recent advancement in high-k and metal gate (HK+MG) technology has allowed improvements in gate control owing to the aggressive scaling of equivalent oxide thickness (EOT), which has not been possible with conventional SiO ₂/poly-gate technology. To continue to scale CMOS devices and get the full benefit of HK+MG technology, it is important to study how process-induced strain (PIS) interferes with the high-k/metal gate and how the new process should be used to generate an additional source of PIS. This article will describe recent data on the effects of metal gate-induced strain on MOSFET performance and interactions with the conventional PIS technique.