Strain engineering in nanoscale CMOS FinFETs and methods to optimize R S/D

Casey Smith; Srivatsan Parthasarathy; Brian E. Coss; Jason Williams; Hemant Adhikari; Greg Smith; Barry Sassman; Muhammad Mustafa Hussain; Prashant Majhi; Raj Jammy

doi:10.1109/VTSA.2010.5488905

Strain engineering in nanoscale CMOS FinFETs and methods to optimize R _S/D

Casey Smith^*, Srivatsan Parthasarathy, Brian E. Coss, Jason Williams, Hemant Adhikari, Greg Smith, Barry Sassman, Muhammad Mustafa Hussain, Prashant Majhi, Raj Jammy

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

For the first time, we demonstrate stressor contact etch stop liner (sCESL) modulation of parasitics/external resistance in nonplanar devices. We report 17% saturation drive current enhancement in underlap doped cMOS FinFETs attributed to simultaneous lowering of R_S/D via biaxial S/D stress and μ_o increase via effective uniaxial channel stress. Our observations imply that biaxial strain engineering for reduction of R _S/D offers a significant opportunity to realize non-planar CMOSFET performance metrics for the 22nm node and beyond.

Original language	English (US)
Title of host publication	Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages	156-157
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2010.5488905
State	Published - 2010
Event	2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu, Taiwan, Province of China Duration: Apr 26 2010 → Apr 28 2010

Publication series

Name	Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Other

Other	2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Country/Territory	Taiwan, Province of China
City	Hsin Chu
Period	04/26/10 → 04/28/10

Keywords

Biaxial stress
CESL
FinFET
R
Stressor

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/VTSA.2010.5488905

Cite this

Smith, C., Parthasarathy, S., Coss, B. E., Williams, J., Adhikari, H., Smith, G., Sassman, B., Hussain, M. M., Majhi, P., & Jammy, R. (2010). Strain engineering in nanoscale CMOS FinFETs and methods to optimize R _S/D. In Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 (pp. 156-157). Article 5488905 (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010). https://doi.org/10.1109/VTSA.2010.5488905

@inproceedings{3e0cb0bf29bf467c96e663e3557863db,

title = "Strain engineering in nanoscale CMOS FinFETs and methods to optimize R S/D",

abstract = "For the first time, we demonstrate stressor contact etch stop liner (sCESL) modulation of parasitics/external resistance in nonplanar devices. We report 17% saturation drive current enhancement in underlap doped cMOS FinFETs attributed to simultaneous lowering of RS/D via biaxial S/D stress and μo increase via effective uniaxial channel stress. Our observations imply that biaxial strain engineering for reduction of R S/D offers a significant opportunity to realize non-planar CMOSFET performance metrics for the 22nm node and beyond.",

keywords = "Biaxial stress, CESL, FinFET, R, Stressor",

author = "Casey Smith and Srivatsan Parthasarathy and Coss, {Brian E.} and Jason Williams and Hemant Adhikari and Greg Smith and Barry Sassman and Hussain, {Muhammad Mustafa} and Prashant Majhi and Raj Jammy",

year = "2010",

doi = "10.1109/VTSA.2010.5488905",

language = "English (US)",

isbn = "9781424450633",

series = "Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010",

pages = "156--157",

booktitle = "Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010",

note = "2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 ; Conference date: 26-04-2010 Through 28-04-2010",

}

Smith, C, Parthasarathy, S, Coss, BE, Williams, J, Adhikari, H, Smith, G, Sassman, B, Hussain, MM, Majhi, P & Jammy, R 2010, Strain engineering in nanoscale CMOS FinFETs and methods to optimize R _S/D. in Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010., 5488905, Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010, pp. 156-157, 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010, Hsin Chu, Taiwan, Province of China, 04/26/10. https://doi.org/10.1109/VTSA.2010.5488905

Strain engineering in nanoscale CMOS FinFETs and methods to optimize R _S/D. / Smith, Casey; Parthasarathy, Srivatsan; Coss, Brian E. et al.
Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. p. 156-157 5488905 (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Smith, Casey

AU - Parthasarathy, Srivatsan

AU - Coss, Brian E.

AU - Williams, Jason

AU - Adhikari, Hemant

AU - Smith, Greg

AU - Sassman, Barry

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AU - Majhi, Prashant

AU - Jammy, Raj

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AB - For the first time, we demonstrate stressor contact etch stop liner (sCESL) modulation of parasitics/external resistance in nonplanar devices. We report 17% saturation drive current enhancement in underlap doped cMOS FinFETs attributed to simultaneous lowering of RS/D via biaxial S/D stress and μo increase via effective uniaxial channel stress. Our observations imply that biaxial strain engineering for reduction of R S/D offers a significant opportunity to realize non-planar CMOSFET performance metrics for the 22nm node and beyond.

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Smith C, Parthasarathy S, Coss BE, Williams J, Adhikari H, Smith G et al. Strain engineering in nanoscale CMOS FinFETs and methods to optimize R _S/D. In Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. p. 156-157. 5488905. (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010). doi: 10.1109/VTSA.2010.5488905