Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

Luca Pirro; Amer El Hajj Diab; Irina Ionica; Gerard Ghibaudo; Lorenzo Faraone; Sorin Cristoloveanu

doi:10.1109/ted.2015.2454438

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

Luca Pirro, Amer El Hajj Diab, Irina Ionica, Gerard Ghibaudo, Lorenzo Faraone, Sorin Cristoloveanu

Computer, Electrical and Mathematical Sciences and Engineering

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Original language	English (US)
Pages (from-to)	2717-2723
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	62
Issue number	9
DOIs	https://doi.org/10.1109/ted.2015.2454438
State	Published - Sep 2015

Bibliographical note

KAUST Repository Item: Exported on 2020-10-01
Acknowledgements: Soitec, Bernin, France

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title = "Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration",

abstract = "Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. {\textcopyright} 1963-2012 IEEE.",

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AU - Pirro, Luca

AU - Diab, Amer El Hajj

AU - Ionica, Irina

AU - Ghibaudo, Gerard

AU - Faraone, Lorenzo

AU - Cristoloveanu, Sorin

N1 - KAUST Repository Item: Exported on 2020-10-01 Acknowledgements: Soitec, Bernin, France

PY - 2015/9

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N2 - Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

AB - Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

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Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

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