Scalable Complementary FeFET CAM Design

O. Bekdache, H. Nour Eddine, M. Al Tawil, R. Kanj, M. E. Fouda, Ahmed Eltawil

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

CAMs are frequently employed for data-centric applications. They offer excellent parallelism. Traditionally, they were implemented using the area-consuming SRAM. Recent advancements suggest using compact nonvolatile memories (NVMs) to create CAM cells to reduce area. The ferroelectric field effect transistor (FeFET) has therefore emerged as an NVM device showing great potential in these memory architectures. In this work, we propose a novel multi-bit CAM architecture that utilizes p-type FeFETs – a topic yet to be explored in the literature – and we compare the latency, accuracy, and energy consumption of our design to other FeFET-based architectures demonstrating a 3-30× reduction in fail probability.
Original languageEnglish (US)
Title of host publication2023 IEEE International Symposium on Circuits and Systems (ISCAS)
PublisherIEEE
DOIs
StatePublished - Jul 21 2023

Bibliographical note

KAUST Repository Item: Exported on 2023-07-25

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