This paper investigates the impact of scalability on h-BN based memristors, with a focus on yield and variability. Motivated by the atomic-defect-enabled operation mechanism of h-BN memristors, a stochastic geometry modelling framework is employed to characterize the distribution of atomic defects across a large array of devices. This is coupled with a probabilistic defect activation model to characterize the SET voltage. The model is benchmarked to experimental results for monolayer and multi-layer h-BN devices. The presented results highlight the profound impact of scalability on device yield, device-to-device variability and SET voltage.