RPN oxynitride gate dielectrics for 90nm low power CMOS applications

A. Veloso; M. Jurczak; F. N. Cubaynes; R. Rooyackers; S. Mertens; A. Rothschild; M. Schaekers; H. N. Al-Shareef; R. W. Murto; C. J.J. Dachs; G. Badenes

doi:10.1109/ESSDERC.2002.194894

RPN oxynitride gate dielectrics for 90nm low power CMOS applications

A. Veloso^*, M. Jurczak, F. N. Cubaynes, R. Rooyackers, S. Mertens, A. Rothschild, M. Schaekers, H. N. Al-Shareef, R. W. Murto, C. J.J. Dachs, G. Badenes

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the I_OFF current of 20 pA/μm and improve the I_ON-I_OFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 μA/μm (at IOFF =16 pA/μm) and 170 μA/μm (at IOFF =16 pA/μm), respectively. The obtained results are among the best values reported in the literature.

Original language	English (US)
Title of host publication	European Solid-State Device Research Conference
Editors	Elena Gnani, Giorgio Baccarani, Massimo Rudan
Publisher	IEEE Computer Society
Pages	159-162
Number of pages	4
ISBN (Electronic)	8890084782
DOIs	https://doi.org/10.1109/ESSDERC.2002.194894
State	Published - 2002
Externally published	Yes
Event	32nd European Solid-State Device Research Conference, ESSDERC 2002 - Firenze, Italy Duration: Sep 24 2002 → Sep 26 2002

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Other

Other	32nd European Solid-State Device Research Conference, ESSDERC 2002
Country/Territory	Italy
City	Firenze
Period	09/24/02 → 09/26/02

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

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10.1109/ESSDERC.2002.194894

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Veloso, A., Jurczak, M., Cubaynes, F. N., Rooyackers, R., Mertens, S., Rothschild, A., Schaekers, M., Al-Shareef, H. N., Murto, R. W., Dachs, C. J. J., & Badenes, G. (2002). RPN oxynitride gate dielectrics for 90nm low power CMOS applications. In E. Gnani, G. Baccarani, & M. Rudan (Eds.), European Solid-State Device Research Conference (pp. 159-162). (European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2002.194894

@inproceedings{1147965c4f5e4648bf8b51a1fb608603,

title = "RPN oxynitride gate dielectrics for 90nm low power CMOS applications",

abstract = "This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the IOFF current of 20 pA/μm and improve the ION-IOFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 μA/μm (at IOFF =16 pA/μm) and 170 μA/μm (at IOFF =16 pA/μm), respectively. The obtained results are among the best values reported in the literature.",

author = "A. Veloso and M. Jurczak and Cubaynes, {F. N.} and R. Rooyackers and S. Mertens and A. Rothschild and M. Schaekers and Al-Shareef, {H. N.} and Murto, {R. W.} and Dachs, {C. J.J.} and G. Badenes",

year = "2002",

doi = "10.1109/ESSDERC.2002.194894",

language = "English (US)",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "159--162",

editor = "Elena Gnani and Giorgio Baccarani and Massimo Rudan",

booktitle = "European Solid-State Device Research Conference",

address = "United States",

note = "32nd European Solid-State Device Research Conference, ESSDERC 2002 ; Conference date: 24-09-2002 Through 26-09-2002",

}

Veloso, A, Jurczak, M, Cubaynes, FN, Rooyackers, R, Mertens, S, Rothschild, A, Schaekers, M, Al-Shareef, HN, Murto, RW, Dachs, CJJ & Badenes, G 2002, RPN oxynitride gate dielectrics for 90nm low power CMOS applications. in E Gnani, G Baccarani & M Rudan (eds), European Solid-State Device Research Conference. European Solid-State Device Research Conference, IEEE Computer Society, pp. 159-162, 32nd European Solid-State Device Research Conference, ESSDERC 2002, Firenze, Italy, 09/24/02. https://doi.org/10.1109/ESSDERC.2002.194894

RPN oxynitride gate dielectrics for 90nm low power CMOS applications. / Veloso, A.; Jurczak, M.; Cubaynes, F. N. et al.
European Solid-State Device Research Conference. ed. / Elena Gnani; Giorgio Baccarani; Massimo Rudan. IEEE Computer Society, 2002. p. 159-162 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - RPN oxynitride gate dielectrics for 90nm low power CMOS applications

AU - Veloso, A.

AU - Jurczak, M.

AU - Cubaynes, F. N.

AU - Rooyackers, R.

AU - Mertens, S.

AU - Rothschild, A.

AU - Schaekers, M.

AU - Al-Shareef, H. N.

AU - Murto, R. W.

AU - Dachs, C. J.J.

AU - Badenes, G.

PY - 2002

Y1 - 2002

N2 - This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the IOFF current of 20 pA/μm and improve the ION-IOFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 μA/μm (at IOFF =16 pA/μm) and 170 μA/μm (at IOFF =16 pA/μm), respectively. The obtained results are among the best values reported in the literature.

AB - This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the IOFF current of 20 pA/μm and improve the ION-IOFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 μA/μm (at IOFF =16 pA/μm) and 170 μA/μm (at IOFF =16 pA/μm), respectively. The obtained results are among the best values reported in the literature.

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U2 - 10.1109/ESSDERC.2002.194894

DO - 10.1109/ESSDERC.2002.194894

M3 - Conference contribution

AN - SCOPUS:84907688487

T3 - European Solid-State Device Research Conference

SP - 159

EP - 162

BT - European Solid-State Device Research Conference

A2 - Gnani, Elena

A2 - Baccarani, Giorgio

A2 - Rudan, Massimo

PB - IEEE Computer Society

T2 - 32nd European Solid-State Device Research Conference, ESSDERC 2002

Y2 - 24 September 2002 through 26 September 2002

ER -

RPN oxynitride gate dielectrics for 90nm low power CMOS applications

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