TY - GEN
T1 - Reliability analysis for on-chip networks under RC interconnect delay variation
AU - Mondal, Mosin
AU - Wu, Xiang
AU - Aziz, Adrian
AU - Massoud, Yehia
N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13
PY - 2006/12/1
Y1 - 2006/12/1
N2 - Future integrated circuits will be characterized by their high defect rates thereby necessitating certain degree of redundancy. In a typical Network-on-Chip (NoC), multiple paths exist between a source and a sink to provide the required level of fault tolerance. Consequently, a manufacturing fault on a single interconnect does not necessarily render the resulting integrated circuit useless. In this paper we quantify the fault tolerance offered by an NoC. Specifically, we (1) provide a model for determining the probability that an NoC link fails due to manufacturing variation, and (2) measure the impact of link failure on the number of cycles taken by the NoC to implement communication. ©2006 IEEE.
AB - Future integrated circuits will be characterized by their high defect rates thereby necessitating certain degree of redundancy. In a typical Network-on-Chip (NoC), multiple paths exist between a source and a sink to provide the required level of fault tolerance. Consequently, a manufacturing fault on a single interconnect does not necessarily render the resulting integrated circuit useless. In this paper we quantify the fault tolerance offered by an NoC. Specifically, we (1) provide a model for determining the probability that an NoC link fails due to manufacturing variation, and (2) measure the impact of link failure on the number of cycles taken by the NoC to implement communication. ©2006 IEEE.
UR - http://ieeexplore.ieee.org/document/4152821/
UR - http://www.scopus.com/inward/record.url?scp=50149107267&partnerID=8YFLogxK
U2 - 10.1109/NANONET.2006.346238
DO - 10.1109/NANONET.2006.346238
M3 - Conference contribution
SN - 142440391X
BT - 2006 1st International Conference on Nano-Networks and Workshops, Nano-Net
ER -