Reliability analysis for on-chip networks under RC interconnect delay variation

Mosin Mondal, Xiang Wu, Adrian Aziz, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations


Future integrated circuits will be characterized by their high defect rates thereby necessitating certain degree of redundancy. In a typical Network-on-Chip (NoC), multiple paths exist between a source and a sink to provide the required level of fault tolerance. Consequently, a manufacturing fault on a single interconnect does not necessarily render the resulting integrated circuit useless. In this paper we quantify the fault tolerance offered by an NoC. Specifically, we (1) provide a model for determining the probability that an NoC link fails due to manufacturing variation, and (2) measure the impact of link failure on the number of cycles taken by the NoC to implement communication. ©2006 IEEE.
Original languageEnglish (US)
Title of host publication2006 1st International Conference on Nano-Networks and Workshops, Nano-Net
StatePublished - Dec 1 2006
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2022-09-13


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