Reduced hot-carrier induced degradation of NMOS I/O transistors with sub-micron source-drain diffusion length for 0.11 μm dual gate oxide CMOS technology

Kwang Seng See*, Wai Shing Lau, Suey Li Toh, Hong Liao, Jae Gon Lee, L. I. Kun, Elgin Kiok Boone Quek, Kheng Chok Tee, Lap Hung Chan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

The effect of reduced source-drain diffusion length (Lov) on hot-carrier induced degradation of NMOS I/O transistors using 0.11 μm dual gate oxide (DGO) complementary metal oxide semiconductor (CMOS) technology will be reported. An understanding of hot-carrier induced degradation would be very important for modern DGO CMOS integrated circuits. And since hot carrier degradation is usually more serious in n-channel metal oxide semiconductor (NMOS) transistors, we will focus our discussion on the effect of Lov reduction on hot-carrier induced degradation in n-channel thick gate oxide I/O MOS transistors. It is discovered that as Lov decreases, which then gives rise to compressive strain in the channel region of the transistor, hot-carrier induced degradation in NMOS I/O transistors is reduced. Direct-current current-voltage (DCIV) spectrum suggests that no additional, interface traps (ΔNit) generation or charge trapping was created when using shorter Lov S.

Original languageEnglish (US)
Pages (from-to)2125-2131
Number of pages7
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume44
Issue number4 B
DOIs
StatePublished - Apr 2005
Externally publishedYes

Keywords

  • Charge trapping
  • Direct-current current-voltage (DCIV)
  • Dual gate oxide (DGO)
  • Hot-carrier induced degradation
  • Interface trap
  • NMOS

ASJC Scopus subject areas

  • General Engineering
  • General Physics and Astronomy

Fingerprint

Dive into the research topics of 'Reduced hot-carrier induced degradation of NMOS I/O transistors with sub-micron source-drain diffusion length for 0.11 μm dual gate oxide CMOS technology'. Together they form a unique fingerprint.

Cite this