Abstract
In this paper, we present a fully digital differential chaos based random number generator. The output of the digital circuit is proved to be chaotic by calculating the output time series maximum Lyapunov exponent. We introduce a new post processing technique to improve the distribution and statistical properties of the generated data. The post-processed output passes the NIST Sp. 800-22 statistical tests. The system is written in Verilog VHDL and realized on Xilinx Virtex® FPGA. The generator can fit into a very small area and have a maximum throughput of 2.1 Gb/s.
Original language | English (US) |
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Title of host publication | 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
ISBN (Print) | 9781612848563 |
DOIs | |
State | Published - Sep 28 2011 |