Programmable Memristive Threshold Logic Gate Array

Olga Krestinskaya, Akshay Kumar Maan, Alex Pappachen James

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.
Original languageEnglish (US)
Title of host publication2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)9781538682401
StatePublished - Jan 8 2019
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2023-09-23


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