Programmable Memristive Threshold Logic Gate Array

Olga Krestinskaya; Akshay Kumar Maan; Alex Pappachen James

doi:10.1109/APCCAS.2018.8605646

Programmable Memristive Threshold Logic Gate Array

Olga Krestinskaya, Akshay Kumar Maan, Alex Pappachen James

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.

Original language	English (US)
Title of host publication	2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	313-316
Number of pages	4
ISBN (Print)	9781538682401
DOIs	https://doi.org/10.1109/APCCAS.2018.8605646
State	Published - Jan 8 2019
Externally published	Yes

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Generated from Scopus record by KAUST IRTS on 2023-09-23

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10.1109/APCCAS.2018.8605646

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title = "Programmable Memristive Threshold Logic Gate Array",

abstract = "This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.",

author = "Olga Krestinskaya and Maan, {Akshay Kumar} and James, {Alex Pappachen}",

note = "Generated from Scopus record by KAUST IRTS on 2023-09-23",

year = "2019",

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doi = "10.1109/APCCAS.2018.8605646",

language = "English (US)",

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T1 - Programmable Memristive Threshold Logic Gate Array

AU - Krestinskaya, Olga

AU - Maan, Akshay Kumar

AU - James, Alex Pappachen

N1 - Generated from Scopus record by KAUST IRTS on 2023-09-23

PY - 2019/1/8

Y1 - 2019/1/8

N2 - This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.

AB - This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.

UR - https://ieeexplore.ieee.org/document/8605646/

UR - http://www.scopus.com/inward/record.url?scp=85062229906&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2018.8605646

DO - 10.1109/APCCAS.2018.8605646

M3 - Conference contribution

SN - 9781538682401

SP - 313

EP - 316

BT - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Programmable Memristive Threshold Logic Gate Array

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