Process variations-aware resistive associative processor design

Hasan Erdem Yantir; Mohammed E. Fouda; Ahmed M. Eltawil; Fadi J. Kurdahi

doi:10.1109/ICCD.2016.7753260

Process variations-aware resistive associative processor design

Hasan Erdem Yantir, Mohammed E. Fouda, Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

Recent breakthroughs in memristive devices have demonstrated the potential of using resistive content addressable memories for associative processing. These architectures enable ultra-high density integrated circuits along with low-power computation. However, the reliability of memristive elements is limiting the widespread adoption of these architectures. In this study, we address the reliability issues that arise in high density, resistive associative processor architectures. We propose methods to design process variation immune resistive content addressable memories and minimize the error probabilities. According to SPICE-based circuit simulations, the reliability of the circuit increases significantly and thus positively influences the accuracy of arithmetic operations as well.

Original language	English (US)
Title of host publication	Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781509051427
DOIs	https://doi.org/10.1109/ICCD.2016.7753260
State	Published - Nov 22 2016
Externally published	Yes

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Generated from Scopus record by KAUST IRTS on 2019-11-20

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@inproceedings{377de07e547947a6acc5026f283afe9c,

title = "Process variations-aware resistive associative processor design",

abstract = "Recent breakthroughs in memristive devices have demonstrated the potential of using resistive content addressable memories for associative processing. These architectures enable ultra-high density integrated circuits along with low-power computation. However, the reliability of memristive elements is limiting the widespread adoption of these architectures. In this study, we address the reliability issues that arise in high density, resistive associative processor architectures. We propose methods to design process variation immune resistive content addressable memories and minimize the error probabilities. According to SPICE-based circuit simulations, the reliability of the circuit increases significantly and thus positively influences the accuracy of arithmetic operations as well.",

author = "Yantir, {Hasan Erdem} and Fouda, {Mohammed E.} and Eltawil, {Ahmed M.} and Kurdahi, {Fadi J.}",

note = "Generated from Scopus record by KAUST IRTS on 2019-11-20",

year = "2016",

month = nov,

day = "22",

doi = "10.1109/ICCD.2016.7753260",

language = "English (US)",

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booktitle = "Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016",

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T1 - Process variations-aware resistive associative processor design

AU - Yantir, Hasan Erdem

AU - Fouda, Mohammed E.

AU - Eltawil, Ahmed M.

AU - Kurdahi, Fadi J.

N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20

PY - 2016/11/22

Y1 - 2016/11/22

N2 - Recent breakthroughs in memristive devices have demonstrated the potential of using resistive content addressable memories for associative processing. These architectures enable ultra-high density integrated circuits along with low-power computation. However, the reliability of memristive elements is limiting the widespread adoption of these architectures. In this study, we address the reliability issues that arise in high density, resistive associative processor architectures. We propose methods to design process variation immune resistive content addressable memories and minimize the error probabilities. According to SPICE-based circuit simulations, the reliability of the circuit increases significantly and thus positively influences the accuracy of arithmetic operations as well.

AB - Recent breakthroughs in memristive devices have demonstrated the potential of using resistive content addressable memories for associative processing. These architectures enable ultra-high density integrated circuits along with low-power computation. However, the reliability of memristive elements is limiting the widespread adoption of these architectures. In this study, we address the reliability issues that arise in high density, resistive associative processor architectures. We propose methods to design process variation immune resistive content addressable memories and minimize the error probabilities. According to SPICE-based circuit simulations, the reliability of the circuit increases significantly and thus positively influences the accuracy of arithmetic operations as well.

UR - http://ieeexplore.ieee.org/document/7753260/

UR - http://www.scopus.com/inward/record.url?scp=85006729176&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2016.7753260

DO - 10.1109/ICCD.2016.7753260

M3 - Conference contribution

SN - 9781509051427

BT - Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Process variations-aware resistive associative processor design

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