TY - GEN
T1 - Privacy-preserving functional IP verification utilizing fully homomorphic encryption
AU - Konstantinou, Charalambos
AU - Keliris, Anastasis
AU - Maniatakos, Michail
N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13
PY - 2015/4/22
Y1 - 2015/4/22
N2 - Intellectual Property (IP) verification is a crucial component of System-on-Chip (SoC) design in the modern IC design business model. Given a globalized supply chain and an increasing demand for IP reuse, IP theft has become a major concern for the IC industry. In this paper, we address the trust issues that arise between IP owners and IP users during the functional verification of an IP core. Our proposed scheme ensures the privacy of IP owners and users, by a) generating a privacy-preserving version of the IP, which is functionally equivalent to the original design, and b) employing homomorphically encrypted input vectors. This allows the functional verification to be securely outsourced to a third-party, or to be executed by either parties, while revealing the least possible information regarding the test vectors and the IP core. Experiments on both combinational and sequential benchmark circuits demonstrate up to three orders of magnitude IP verification slowdown, due to the computationally intensive fully homomorphic operations, for different security parameter sizes.
AB - Intellectual Property (IP) verification is a crucial component of System-on-Chip (SoC) design in the modern IC design business model. Given a globalized supply chain and an increasing demand for IP reuse, IP theft has become a major concern for the IC industry. In this paper, we address the trust issues that arise between IP owners and IP users during the functional verification of an IP core. Our proposed scheme ensures the privacy of IP owners and users, by a) generating a privacy-preserving version of the IP, which is functionally equivalent to the original design, and b) employing homomorphically encrypted input vectors. This allows the functional verification to be securely outsourced to a third-party, or to be executed by either parties, while revealing the least possible information regarding the test vectors and the IP core. Experiments on both combinational and sequential benchmark circuits demonstrate up to three orders of magnitude IP verification slowdown, due to the computationally intensive fully homomorphic operations, for different security parameter sizes.
UR - http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7092410
UR - http://www.scopus.com/inward/record.url?scp=84945950660&partnerID=8YFLogxK
U2 - 10.7873/date.2015.1049
DO - 10.7873/date.2015.1049
M3 - Conference contribution
SN - 9783981537048
SP - 333
EP - 338
BT - Proceedings -Design, Automation and Test in Europe, DATE
PB - Institute of Electrical and Electronics Engineers Inc.
ER -