Power-supply-variation-aware timing analysis of synchronous systems

Sami Kirolos, Yehia Massoud, Yehea Ismail

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

With state of the art technology scaling, the problem of delay variability due to power supply variations is becoming more and more critical. This paper addresses the problem of analyzing the speed degradation in synchronous systems caused by power supply IR-drop in deep submicron CMOS devices. Considering the impact of power supply variation on the clock skew value, violations of the timing constraints equations are presented. To satisfy the timing constraints over a range of 20% of VDD variation, a 42% increase in the operational clock period has to be met with circuits operating at 2GHz and implemented on 65nm CMOS technology. ©2008 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages2418-2421
Number of pages4
DOIs
StatePublished - Sep 19 2008
Externally publishedYes

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