Plasma-induced damage in high-formula formula-κ/metal gate stack dry etch

Muhammad Mustafa Hussain*, Seung Chul Song, Joel Barnett, Chang Yong Kang, Gabe Gebara, Barry Sassman, Naim Moumen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


Plasma-based dry etch is used as the industry standard gate etch in conventional CMOS fabrication flow. However, past studies indicate that plasma-induced dry etch may impact device performance. The current research trend toward replacing conventional silicon dioxide and polysilicon gate stacks with high-k/metal gate stacks introduces a new challenge: development of new dry etch processes for critical new metals and their alloys. In this letter, a comparative study in the context of device performance has been conducted to compare dry etch versus wet etch for gate stack etch of hafnium oxide/tantalum silicon nitride gate stack. It has been found that the dry-etched gate stack exhibit significantly more gate leakage current and poorer uniformity in threshold-voltage distribution.

Original languageEnglish (US)
Pages (from-to)972-974
Number of pages3
JournalIEEE Electron Device Letters
Issue number12
StatePublished - Dec 2006
Externally publishedYes


  • Gate-induced drain leakage (GIDL)
  • High-κ/metal gate
  • Plasma dry etch
  • Threshold-voltage
  • Wet etch

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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