As CMOS technology is pushed to its basic physical limits, alternate technologies are required for the realization of interconnect in future high performance integrated circuits. In this paper, we develop a generalized design technique for carbon nanotube (CNT) bundle-based interconnect, which we use to examine the performance limits and fabrication requirements for future nanotube-based interconnect solutions. The results indicate that optimized nanotube bundles can provide up to a 69% delay reduction in 22 nm process technology, and the optimal design method decreases delay by 21% and 29% on average compared to non-optimized multi-walled and single-walled CNT bundles. We also find that future CNT bundle fabrication processes must achieve a nanotube area coverage of at least 30% for optimized CNT bundles and 40% for non-optimized CNT bundles to obtain competitive performance results compared to copper interconnect. ©2008 IEEE.
|Title of host publication
|Proceedings - IEEE International Symposium on Circuits and Systems
|Number of pages
|Published - Sep 19 2008