This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-duration profiles, and can be used to derive a noise susceptibility metric for the noise robustness of logic gates. Analytical methods - based upon calibration runs in circuit simulators - to determine noise susceptibility in the presence of variations in process, design, and environmental parameters (Leff, VT, VDD, and W) are described. Such analytical methods can be used not only to accurately estimate the impact of variability on noise robustness, but also to optimize designs for noise robustness. © 2007 IEEE.
|Original language||English (US)|
|Title of host publication||Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007|
|Number of pages||5|
|State||Published - Aug 28 2007|