Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications

Md Hasan Raza Ansari; Nazek El-Atab

doi:10.1109/EDTM55494.2023.10103084

Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications

Md Hasan Raza Ansari, Nazek El-Atab

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This work validates the synaptic behaviors (long-term potentiation (LTP) and depression (LTD)) of a junctionless transistor (JL) through the simulator. The synaptic transistor is an essential component for implementing artificial neural networks (ANN), which are called hardware neural networks (HNNs). This analysis shows optimization of nonlinearity and dynamic range of conductance values of LTP and LTD and is used for implementing the ANN with the MNIST dataset. The device achieves linear conductance (0.1) value and a higher dynamic range (105) by optimizing the gate voltage. These results indicate that the JL device achieves 88.1 % image recognition accuracy.

Original language	English (US)
Title of host publication	7th IEEE Electron Devices Technology and Manufacturing Conference
Subtitle of host publication	Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350332520
DOIs	https://doi.org/10.1109/EDTM55494.2023.10103084
State	Published - 2023
Event	7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023 - Seoul, Korea, Republic of Duration: Mar 7 2023 → Mar 10 2023

Publication series

Name	7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023

Conference

Conference	7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023
Country/Territory	Korea, Republic of
City	Seoul
Period	03/7/23 → 03/10/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

ANN
Junctionless Transistor
LTD
LTP
Neural Network
STP
Synaptic Transistor

ASJC Scopus subject areas

Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials
Instrumentation
Electrical and Electronic Engineering

Access to Document

10.1109/EDTM55494.2023.10103084

Cite this

Raza Ansari, M. H., & El-Atab, N. (2023). Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications. In 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023 (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM55494.2023.10103084

Raza Ansari, Md Hasan ; El-Atab, Nazek. / Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications. 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023).

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abstract = "This work validates the synaptic behaviors (long-term potentiation (LTP) and depression (LTD)) of a junctionless transistor (JL) through the simulator. The synaptic transistor is an essential component for implementing artificial neural networks (ANN), which are called hardware neural networks (HNNs). This analysis shows optimization of nonlinearity and dynamic range of conductance values of LTP and LTD and is used for implementing the ANN with the MNIST dataset. The device achieves linear conductance (0.1) value and a higher dynamic range (105) by optimizing the gate voltage. These results indicate that the JL device achieves 88.1 % image recognition accuracy.",

keywords = "ANN, Junctionless Transistor, LTD, LTP, Neural Network, STP, Synaptic Transistor",

author = "{Raza Ansari}, {Md Hasan} and Nazek El-Atab",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023 ; Conference date: 07-03-2023 Through 10-03-2023",

year = "2023",

doi = "10.1109/EDTM55494.2023.10103084",

language = "English (US)",

series = "7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023",

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Raza Ansari, MH & El-Atab, N 2023, Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications. in 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023, Institute of Electrical and Electronics Engineers Inc., 7th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2023, Seoul, Korea, Republic of, 03/7/23. https://doi.org/10.1109/EDTM55494.2023.10103084

Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications. / Raza Ansari, Md Hasan; El-Atab, Nazek.
7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Raza Ansari, Md Hasan

AU - El-Atab, Nazek

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N2 - This work validates the synaptic behaviors (long-term potentiation (LTP) and depression (LTD)) of a junctionless transistor (JL) through the simulator. The synaptic transistor is an essential component for implementing artificial neural networks (ANN), which are called hardware neural networks (HNNs). This analysis shows optimization of nonlinearity and dynamic range of conductance values of LTP and LTD and is used for implementing the ANN with the MNIST dataset. The device achieves linear conductance (0.1) value and a higher dynamic range (105) by optimizing the gate voltage. These results indicate that the JL device achieves 88.1 % image recognition accuracy.

AB - This work validates the synaptic behaviors (long-term potentiation (LTP) and depression (LTD)) of a junctionless transistor (JL) through the simulator. The synaptic transistor is an essential component for implementing artificial neural networks (ANN), which are called hardware neural networks (HNNs). This analysis shows optimization of nonlinearity and dynamic range of conductance values of LTP and LTD and is used for implementing the ANN with the MNIST dataset. The device achieves linear conductance (0.1) value and a higher dynamic range (105) by optimizing the gate voltage. These results indicate that the JL device achieves 88.1 % image recognition accuracy.

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Raza Ansari MH, El-Atab N. Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications. In 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023). doi: 10.1109/EDTM55494.2023.10103084

Optimization of Performance Metrics of Charge Trapping Synaptic Device for Neuromorphic Applications

Abstract

Publication series

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Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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