On the impact of traffic statistics on quality of service for networks on chip

Stefano Santi, Bill Lin, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations


Packet switched Networks on Chip (NoC) architectures have been proposed as a solution to the global interconnect problem in the nanoscale Systems on Chip (SoC) design era. An important design consideration for NoC is silicon cost. Towards the goal of keeping the NoC simple, we pose the following question: Under what traffic conditions will Quality of Service (QoS) be provided without the added complexity of an explicit QoS mechanism? In this paper, we take the first step towards answering this question by empirically analyzing different combinations of traffic patterns and injection processes. Specifically, we analyze the effects of different traffic on latency under two cases: (1) An NoC with no QoS mechanism (i.e. without distinction among different classes of service); (2) An NoC with the simplest distinction into two classes of service: guaranteed service and best effort. © 2005 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Number of pages4
StatePublished - Dec 1 2005
Externally publishedYes

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Generated from Scopus record by KAUST IRTS on 2023-02-15


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