TY - GEN
T1 - On the convergence to regime of ADC-based true random number generators
AU - Rovatti, Riccardo
AU - Callegari, Sergio
AU - Setti, Gianluca
N1 - Generated from Scopus record by KAUST IRTS on 2023-02-15
PY - 2007/1/1
Y1 - 2007/1/1
N2 - Reconfigurable circuits alternatively acting as Random Number Generators (RNGs) or Analog to Digital Converters (ADCs) represent a promising approach to true random bit generation since they can provide high quality random values almost for free whenever a system already embeds an ADC. In their usage, one needs to consider that entering the RNG-mode requires some minor interruption of operation, since the internal chaos-based random source gets initialised at the last ADC input. Hence, the first generated values maintain some dependence on a potentially known value and a few dead beats are needed by the chaotic system to reach a regime where this correlation vanishes. This delay has so far been quantified only empirically. Here, a formal bound is provided, with relation to the required performance level and the system noise floor. © 2007 IEEE.
AB - Reconfigurable circuits alternatively acting as Random Number Generators (RNGs) or Analog to Digital Converters (ADCs) represent a promising approach to true random bit generation since they can provide high quality random values almost for free whenever a system already embeds an ADC. In their usage, one needs to consider that entering the RNG-mode requires some minor interruption of operation, since the internal chaos-based random source gets initialised at the last ADC input. Hence, the first generated values maintain some dependence on a potentially known value and a few dead beats are needed by the chaotic system to reach a regime where this correlation vanishes. This delay has so far been quantified only empirically. Here, a formal bound is provided, with relation to the required performance level and the system noise floor. © 2007 IEEE.
UR - http://ieeexplore.ieee.org/document/4529676/
UR - http://www.scopus.com/inward/record.url?scp=49749093993&partnerID=8YFLogxK
U2 - 10.1109/ECCTD.2007.4529676
DO - 10.1109/ECCTD.2007.4529676
M3 - Conference contribution
SN - 1424413427
SP - 635
EP - 638
BT - European Conference on Circuit Theory and Design 2007, ECCTD 2007
PB - IEEE Computer [email protected]
ER -