The most common assumption for chip-level inductance extraction is to restrict the current return path to the closest power or ground lines. This paper shows that this assumption is not necessarily valid for technologies beyond 0.1 μm. The actual inductance can exceed twice the value that is extracted from the model considering only the nearest current return paths. Analytical formulae to predict the worst case self inductance are proposed to deal with the errors that result from this assumption. These equations can be used as metrics to decide the size of inductance extraction window for future CAD tools.
|Original language||English (US)|
|Title of host publication||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|Publisher||IEEE Computer Societyhelp@computer.org|
|Number of pages||4|
|State||Published - Jan 1 2003|