On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond

So Young Kim; Yehia Massoud; S. Simon Wong

doi:10.1109/ISQED.2003.1194766

On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond

So Young Kim, Yehia Massoud, S. Simon Wong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

31 Scopus citations

Abstract

The most common assumption for chip-level inductance extraction is to restrict the current return path to the closest power or ground lines. This paper shows that this assumption is not necessarily valid for technologies beyond 0.1 μm. The actual inductance can exceed twice the value that is extracted from the model considering only the nearest current return paths. Analytical formulae to predict the worst case self inductance are proposed to deal with the errors that result from this assumption. These equations can be used as metrics to decide the size of inductance extraction window for future CAD tools.

Original language	English (US)
Title of host publication	Proceedings - International Symposium on Quality Electronic Design, ISQED
Publisher	IEEE Computer [email protected]
Pages	401-404
Number of pages	4
ISBN (Print)	0769518818
DOIs	https://doi.org/10.1109/ISQED.2003.1194766
State	Published - Jan 1 2003
Externally published	Yes

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Generated from Scopus record by KAUST IRTS on 2022-09-13

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10.1109/ISQED.2003.1194766

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abstract = "The most common assumption for chip-level inductance extraction is to restrict the current return path to the closest power or ground lines. This paper shows that this assumption is not necessarily valid for technologies beyond 0.1 μm. The actual inductance can exceed twice the value that is extracted from the model considering only the nearest current return paths. Analytical formulae to predict the worst case self inductance are proposed to deal with the errors that result from this assumption. These equations can be used as metrics to decide the size of inductance extraction window for future CAD tools.",

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On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond. / Kim, So Young; Massoud, Yehia; Wong, S. Simon.
Proceedings - International Symposium on Quality Electronic Design, ISQED. IEEE Computer [email protected], 2003. p. 401-404.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Wong, S. Simon

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AB - The most common assumption for chip-level inductance extraction is to restrict the current return path to the closest power or ground lines. This paper shows that this assumption is not necessarily valid for technologies beyond 0.1 μm. The actual inductance can exceed twice the value that is extracted from the model considering only the nearest current return paths. Analytical formulae to predict the worst case self inductance are proposed to deal with the errors that result from this assumption. These equations can be used as metrics to decide the size of inductance extraction window for future CAD tools.

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BT - Proceedings - International Symposium on Quality Electronic Design, ISQED

PB - IEEE Computer [email protected]

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On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond

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