The implementation of analog multiplication process in analog domain is a challenging task, which involves complex circuits with large on-chip area and high power consumption to achieve highly linear multiplication performance. Therefore, such multipliers cannot be used for large scale problems. This paper addresses these issues and proposes four quadrant analog CMOS-memristive analog multiplier design aiming to reduce on-chip area and power consumption of the circuit. The multiplier is designed using TSMC 180 nm CMOS technology and simulated in SPICE. The proposed multiplier allows to reduce on-chip area and power consumption by 25% and 5%, respectively.
|Original language||English (US)|
|Number of pages||5|
|Journal||Proceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018|
|State||Published - Sep 28 2018|