Nanoscale and device level gate conduction variability of high-k dielectrics-based metal-oxide-semiconductor structures

Albin Bayerl; Mario Lanza; Marc Porti; Montserrat Nafria; Xavier Aymerich; F. Campabadal; Gnther Benstetter

doi:10.1109/TDMR.2011.2161087

Nanoscale and device level gate conduction variability of high-k dielectrics-based metal-oxide-semiconductor structures

Albin Bayerl, Mario Lanza, Marc Porti, Montserrat Nafria, Xavier Aymerich, F. Campabadal, Gnther Benstetter

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

The polycrystalline microstructure of the high-k dielectric of gate stacks in metal-oxide-semiconductor (MOS) devices can be a potential source of variability. In this paper, a conductive atomic force microscope (CAFM) and a Kelvin probe force microscope (KPFM) have been used to investigate how the thickness and the crystallization (after a thermal annealing) of the high-k layer affect the nanoscale morphological and electrical properties of the gate stack. The impact of such nanoscale properties on the reliability and variability of the global gate electrical characteristics of fully processed MOS devices has also been investigated. © 2010 IEEE.

Original language	English (US)
Pages (from-to)	495-501
Number of pages	7
Journal	IEEE Transactions on Device and Materials Reliability
Volume	11
Issue number	3
DOIs	https://doi.org/10.1109/TDMR.2011.2161087
State	Published - Sep 1 2011
Externally published	Yes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2021-03-16

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/TDMR.2011.2161087

Cite this

@article{7a204f231b5341c8983be1b128009554,

title = "Nanoscale and device level gate conduction variability of high-k dielectrics-based metal-oxide-semiconductor structures",

abstract = "The polycrystalline microstructure of the high-k dielectric of gate stacks in metal-oxide-semiconductor (MOS) devices can be a potential source of variability. In this paper, a conductive atomic force microscope (CAFM) and a Kelvin probe force microscope (KPFM) have been used to investigate how the thickness and the crystallization (after a thermal annealing) of the high-k layer affect the nanoscale morphological and electrical properties of the gate stack. The impact of such nanoscale properties on the reliability and variability of the global gate electrical characteristics of fully processed MOS devices has also been investigated. {\textcopyright} 2010 IEEE.",

author = "Albin Bayerl and Mario Lanza and Marc Porti and Montserrat Nafria and Xavier Aymerich and F. Campabadal and Gnther Benstetter",

note = "Generated from Scopus record by KAUST IRTS on 2021-03-16",

year = "2011",

month = sep,

day = "1",

doi = "10.1109/TDMR.2011.2161087",

language = "English (US)",

volume = "11",

pages = "495--501",

journal = "IEEE Transactions on Device and Materials Reliability",

issn = "1530-4388",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Nanoscale and device level gate conduction variability of high-k dielectrics-based metal-oxide-semiconductor structures

AU - Bayerl, Albin

AU - Lanza, Mario

AU - Porti, Marc

AU - Nafria, Montserrat

AU - Aymerich, Xavier

AU - Campabadal, F.

AU - Benstetter, Gnther

N1 - Generated from Scopus record by KAUST IRTS on 2021-03-16

PY - 2011/9/1

Y1 - 2011/9/1

N2 - The polycrystalline microstructure of the high-k dielectric of gate stacks in metal-oxide-semiconductor (MOS) devices can be a potential source of variability. In this paper, a conductive atomic force microscope (CAFM) and a Kelvin probe force microscope (KPFM) have been used to investigate how the thickness and the crystallization (after a thermal annealing) of the high-k layer affect the nanoscale morphological and electrical properties of the gate stack. The impact of such nanoscale properties on the reliability and variability of the global gate electrical characteristics of fully processed MOS devices has also been investigated. © 2010 IEEE.

AB - The polycrystalline microstructure of the high-k dielectric of gate stacks in metal-oxide-semiconductor (MOS) devices can be a potential source of variability. In this paper, a conductive atomic force microscope (CAFM) and a Kelvin probe force microscope (KPFM) have been used to investigate how the thickness and the crystallization (after a thermal annealing) of the high-k layer affect the nanoscale morphological and electrical properties of the gate stack. The impact of such nanoscale properties on the reliability and variability of the global gate electrical characteristics of fully processed MOS devices has also been investigated. © 2010 IEEE.

UR - http://ieeexplore.ieee.org/document/5936690/

UR - http://www.scopus.com/inward/record.url?scp=80052610994&partnerID=8YFLogxK

U2 - 10.1109/TDMR.2011.2161087

DO - 10.1109/TDMR.2011.2161087

M3 - Article

SN - 1530-4388

VL - 11

SP - 495

EP - 501

JO - IEEE Transactions on Device and Materials Reliability

JF - IEEE Transactions on Device and Materials Reliability

IS - 3

ER -

Nanoscale and device level gate conduction variability of high-k dielectrics-based metal-oxide-semiconductor structures

Abstract

Bibliographical note

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this