Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process

Youngbae Son; Brad Frost; Yunkai Zhao; Rebecca L. Peterson

doi:10.1038/s41928-019-0316-0

Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process

Youngbae Son, Brad Frost, Yunkai Zhao, Rebecca L. Peterson

Research output: Contribution to journal › Article › peer-review

74 Scopus citations

Abstract

The performance of silicon complementary metal–oxide–semiconductor integrated circuits can be enhanced through the monolithic three-dimensional integration of additional device layers. For example, silicon integrated circuits operate at low voltages (around 1 V) and high-voltage handling capabilities could be provided by monolithically integrating thin-film transistors. Here we show that high-voltage amorphous oxide semiconductor thin-film transistors can be integrated on top of a silicon integrated circuit containing 100-nm-node fin field-effect transistors using an in-air solution process. To solve the problem of voltage mismatch between these two device layers, we use a top Schottky, bottom ohmic contact structure to reduce the amorphous oxide semiconductor circuit switching voltage. These contacts are used to form Schottky-gated thin-film transistors and vertical thin-film diodes with excellent switching performance. As a result, we can create high-voltage amorphous oxide semiconductor circuits with switching voltages less than 1.2 V that can be directly integrated with silicon integrated circuits.

Original language	English (US)
Pages (from-to)	540-548
Number of pages	9
Journal	Nature Electronics
Volume	2
Issue number	11
DOIs	https://doi.org/10.1038/s41928-019-0316-0
State	Published - Nov 18 2019
Externally published	Yes

Bibliographical note

KAUST Repository Item: Exported on 2022-06-13
Acknowledgements: We thank G. A. Torres Sevilla and M. M. Hussain of King Abdullah University of Science and Technology for providing the silicon CMOS samples. We also gratefully acknowledge the contributions of W. Hu, J. Li and J. Miller to TFT fabrication. This work was supported by SPAWAR through DARPA Young Faculty Award N66001-14-1-4046 under D. Green and Y.-K. Chen. Any opinions, findings, conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of DARPA or SPAWAR. Y.S. was supported in part by the Kwanjeong Educational Foundation. Portions of the work reported here were performed in the Lurie Nanofabrication Facility and Michigan Center for Materials Characterization, which are supported by the University of Michigan’s College of Engineering.
This publication acknowledges KAUST support, but has no KAUST affiliated authors.

Access to Document

10.1038/s41928-019-0316-0

Cite this

@article{2ecf76f031344ef5bcbb4057077dedaf,

title = "Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process",

abstract = "The performance of silicon complementary metal–oxide–semiconductor integrated circuits can be enhanced through the monolithic three-dimensional integration of additional device layers. For example, silicon integrated circuits operate at low voltages (around 1 V) and high-voltage handling capabilities could be provided by monolithically integrating thin-film transistors. Here we show that high-voltage amorphous oxide semiconductor thin-film transistors can be integrated on top of a silicon integrated circuit containing 100-nm-node fin field-effect transistors using an in-air solution process. To solve the problem of voltage mismatch between these two device layers, we use a top Schottky, bottom ohmic contact structure to reduce the amorphous oxide semiconductor circuit switching voltage. These contacts are used to form Schottky-gated thin-film transistors and vertical thin-film diodes with excellent switching performance. As a result, we can create high-voltage amorphous oxide semiconductor circuits with switching voltages less than 1.2 V that can be directly integrated with silicon integrated circuits.",

author = "Youngbae Son and Brad Frost and Yunkai Zhao and Peterson, {Rebecca L.}",

note = "KAUST Repository Item: Exported on 2022-06-13 Acknowledgements: We thank G. A. Torres Sevilla and M. M. Hussain of King Abdullah University of Science and Technology for providing the silicon CMOS samples. We also gratefully acknowledge the contributions of W. Hu, J. Li and J. Miller to TFT fabrication. This work was supported by SPAWAR through DARPA Young Faculty Award N66001-14-1-4046 under D. Green and Y.-K. Chen. Any opinions, findings, conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of DARPA or SPAWAR. Y.S. was supported in part by the Kwanjeong Educational Foundation. Portions of the work reported here were performed in the Lurie Nanofabrication Facility and Michigan Center for Materials Characterization, which are supported by the University of Michigan{\textquoteright}s College of Engineering. This publication acknowledges KAUST support, but has no KAUST affiliated authors.",

year = "2019",

month = nov,

day = "18",

doi = "10.1038/s41928-019-0316-0",

language = "English (US)",

volume = "2",

pages = "540--548",

journal = "Nature Electronics",

issn = "2520-1131",

publisher = "Nature Publishing Group",

number = "11",

}

TY - JOUR

T1 - Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process

AU - Son, Youngbae

AU - Frost, Brad

AU - Zhao, Yunkai

AU - Peterson, Rebecca L.

N1 - KAUST Repository Item: Exported on 2022-06-13 Acknowledgements: We thank G. A. Torres Sevilla and M. M. Hussain of King Abdullah University of Science and Technology for providing the silicon CMOS samples. We also gratefully acknowledge the contributions of W. Hu, J. Li and J. Miller to TFT fabrication. This work was supported by SPAWAR through DARPA Young Faculty Award N66001-14-1-4046 under D. Green and Y.-K. Chen. Any opinions, findings, conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of DARPA or SPAWAR. Y.S. was supported in part by the Kwanjeong Educational Foundation. Portions of the work reported here were performed in the Lurie Nanofabrication Facility and Michigan Center for Materials Characterization, which are supported by the University of Michigan’s College of Engineering. This publication acknowledges KAUST support, but has no KAUST affiliated authors.

PY - 2019/11/18

Y1 - 2019/11/18

N2 - The performance of silicon complementary metal–oxide–semiconductor integrated circuits can be enhanced through the monolithic three-dimensional integration of additional device layers. For example, silicon integrated circuits operate at low voltages (around 1 V) and high-voltage handling capabilities could be provided by monolithically integrating thin-film transistors. Here we show that high-voltage amorphous oxide semiconductor thin-film transistors can be integrated on top of a silicon integrated circuit containing 100-nm-node fin field-effect transistors using an in-air solution process. To solve the problem of voltage mismatch between these two device layers, we use a top Schottky, bottom ohmic contact structure to reduce the amorphous oxide semiconductor circuit switching voltage. These contacts are used to form Schottky-gated thin-film transistors and vertical thin-film diodes with excellent switching performance. As a result, we can create high-voltage amorphous oxide semiconductor circuits with switching voltages less than 1.2 V that can be directly integrated with silicon integrated circuits.

AB - The performance of silicon complementary metal–oxide–semiconductor integrated circuits can be enhanced through the monolithic three-dimensional integration of additional device layers. For example, silicon integrated circuits operate at low voltages (around 1 V) and high-voltage handling capabilities could be provided by monolithically integrating thin-film transistors. Here we show that high-voltage amorphous oxide semiconductor thin-film transistors can be integrated on top of a silicon integrated circuit containing 100-nm-node fin field-effect transistors using an in-air solution process. To solve the problem of voltage mismatch between these two device layers, we use a top Schottky, bottom ohmic contact structure to reduce the amorphous oxide semiconductor circuit switching voltage. These contacts are used to form Schottky-gated thin-film transistors and vertical thin-film diodes with excellent switching performance. As a result, we can create high-voltage amorphous oxide semiconductor circuits with switching voltages less than 1.2 V that can be directly integrated with silicon integrated circuits.

UR - http://hdl.handle.net/10754/678925

UR - http://www.nature.com/articles/s41928-019-0316-0

UR - http://www.scopus.com/inward/record.url?scp=85075175760&partnerID=8YFLogxK

U2 - 10.1038/s41928-019-0316-0

DO - 10.1038/s41928-019-0316-0

M3 - Article

SN - 2520-1131

VL - 2

SP - 540

EP - 548

JO - Nature Electronics

JF - Nature Electronics

IS - 11

ER -

Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process

Abstract

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this