Mitigating thermal effects on clock skew with dynamically adaptive drivers

Mosin Mondai, Andrew Ricketts, Sami Kirolos, Tamer Ragheb, Greg Link, Vijaykrishnan Narayanan, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations


On-chip temperature gradient emerged as a major design concern for high performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. We investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles. As an effective way of mitigating the clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that with minimal area overhead our adaptive technique is capable of reducing the skew by 72.4%, on the average, leading to much improved clock synchronization and design performance. © 2007 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
Number of pages6
StatePublished - Aug 28 2007
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2022-09-13


Dive into the research topics of 'Mitigating thermal effects on clock skew with dynamically adaptive drivers'. Together they form a unique fingerprint.

Cite this