Mitigating power-supply induced delay variations using self adjusting clock buffers

Keyphrases

• Supply Variation 100%
• Clock Distribution Network 100%
• Induced Delay 100%
• Clock Tree Architecture 33%
• Buffer Circuit 33%
• Adaptive Buffer 33%

Computer Science

• Delay Variation 100%
• Clock Distribution Networks 100%
• Clock Skew 66%
• Propagation Delay 33%
• Environmental Variation 33%
• Experimental Result 33%
• Integrated Circuits 33%

Engineering

• Power Supply 100%
• Clock Distribution Networks 100%
• Circuit Design 33%
• Experimental Result 33%
• Integrated Circuit 33%
• Buffer Circuits 33%
• Propagation Delay 33%