Aggressive technology scaling tends to reduce integrated circuits resilience against environmental variations. In this paper, we present an adaptive clock buffer circuit design and an adaptive clock distribution network (CDN) to improve chip performance and reliability in the presence of on-chip power-supply variations. The adaptive buffer provides a supply insensitive propagation delay to minimize the supply variation induced clock skew in clock distribution networks. Experimental results show that our technique reduces supply variation induced clock skew by at least 85% in a typical seven level clock tree architecture as compared to a nonadaptive worst case CDN, which represents up to 40% reduction in cycle time in state of the art processors. ©2008 IEEE.
|Title of host publication
|Midwest Symposium on Circuits and Systems
|Number of pages
|Published - Oct 27 2008