Mitigating power-supply induced delay variations using self adjusting clock buffers

Sami Kirolos, Yehia Massoud, Yehea Ismail

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations


Aggressive technology scaling tends to reduce integrated circuits resilience against environmental variations. In this paper, we present an adaptive clock buffer circuit design and an adaptive clock distribution network (CDN) to improve chip performance and reliability in the presence of on-chip power-supply variations. The adaptive buffer provides a supply insensitive propagation delay to minimize the supply variation induced clock skew in clock distribution networks. Experimental results show that our technique reduces supply variation induced clock skew by at least 85% in a typical seven level clock tree architecture as compared to a nonadaptive worst case CDN, which represents up to 40% reduction in cycle time in state of the art processors. ©2008 IEEE.
Original languageEnglish (US)
Title of host publicationMidwest Symposium on Circuits and Systems
Number of pages4
StatePublished - Oct 27 2008
Externally publishedYes

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Generated from Scopus record by KAUST IRTS on 2022-09-13


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