TY - PAT
T1 - Methods and devices for silicon integrated vertically aligned field effect transistors
AU - Li, Jingqi
N1 - KAUST Repository Item: Exported on 2019-02-13
PY - 2015/11/19
Y1 - 2015/11/19
N2 - Embodiments of the present disclosure provide for vertically aligned CNTFET, methods of making vertically aligned CNTFET, methods of using vertically aligned CNTFET, and the like.
AB - Embodiments of the present disclosure provide for vertically aligned CNTFET, methods of making vertically aligned CNTFET, methods of using vertically aligned CNTFET, and the like.
UR - http://hdl.handle.net/10754/595584
UR - http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220150333282%22.PGNR.&OS=DN/20150333282&RS=DN/20150333282
UR - http://assignment.uspto.gov/#/search?adv=publNum:20150333282
UR - http://www.google.com/patents/US20150333282
UR - http://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=2015333282A1&KC=A1&FT=D
M3 - Patent
M1 - US9318718B2
ER -