Memory-loss resilient controller design for temporal logic constraints

M. Abate, W. Stuckey, L. Lerner, E. Feron, S. Coogan

Research output: Contribution to journalArticlepeer-review


This paper studies the problem of controlling finite nondeterministic transition systems to satisfy constraints given as linear temporal logic properties. A controller architecture is proposed that maps finite fragments of the state trajectory history to control inputs. This approach avoids the standard controller construction that employs an onboard automaton which is fragile to memory loss or errors. In contrast, the proposed architecture requires storing only a finite sequence of previous system states in memory and is therefore resilient to memory loss. In particular, the system will operate unaltered after such a memory-loss event once the system recollects this finite sequence of system states. A generalised algorithm is outlined for controller synthesis in this manner. Additionally, we demonstrate the construction and implementation of such a memory-loss resilient controller through an experimental demonstration on a differential-drive robot that experiences memory-loss events.
Original languageEnglish (US)
Pages (from-to)1-22
Number of pages22
JournalCyber-Physical Systems
StatePublished - Oct 24 2020

Bibliographical note

KAUST Repository Item: Exported on 2020-11-04
Acknowledgements: This material is based upon work supported by the United States Government under Contract #W56KGU18C0020 and by the National Science Foundation under award #1749357. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Government.


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