Managing on-chip inductive effects

Yehia Massoud, Steve Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob White

Research output: Contribution to journalArticlepeer-review

61 Scopus citations

Abstract

With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.
Original languageEnglish (US)
Pages (from-to)789-798
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume10
Issue number6
DOIs
StatePublished - Dec 1 2002
Externally publishedYes

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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