Low temperature integration of hybrid CMOS devices on plastic substrates

S. Gowrisanker; M. A. Quevedo-Lopez; H. N. Alshareef; B. Gnade; S. Venugopal; R. Krishna; K. Kaftanoglu; D. Allee

doi:10.1109/FEDC.2009.5069280

Low temperature integration of hybrid CMOS devices on plastic substrates

S. Gowrisanker^*, M. A. Quevedo-Lopez, H. N. Alshareef, B. Gnade, S. Venugopal, R. Krishna, K. Kaftanoglu, D. Allee

^*Corresponding author for this work

Physical Sciences and Engineering

Research output: Contribution to conference › Paper › peer-review

4 Scopus citations

Abstract

The development of flexible Complimentary Metal-Oxide-Semiconductor (CMOS) circuits reduces power consumption by ∼50x compared to n-type (or p-type) only thin film transistor (TFT) digital circuits. In this work we demonstrate a new integration approach to fabricate CMOS circuits on plastic substrates (Poly-ethylene naphthalene, PEN). We use pentacene and amorphous silicon (a-Si:H) thin film transistors for p-type and n-type devices, respectively. The maximum processing temperature for n-type TFTs is 180°C and 120°C for the p-type TFTs. CMOS circuits demonstrated include inverters, NAND and NOR gates. nMOS and pMOS carrier mobility achieved after the CMOS integration process flow are 1.0 and 0.05 cm²/V-s, respectively. Threshold voltages (V_t) are 3.89V for nMOS and -1.89V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates are reported.

Original language	English (US)
DOIs	https://doi.org/10.1109/FEDC.2009.5069280
State	Published - 2009
Event	Flexible Electronics and Displays Conference and Exhibition, FLEX 2009 - Duration: Feb 2 2009 → Feb 2 2009

Other

Other	Flexible Electronics and Displays Conference and Exhibition, FLEX 2009
Period	02/2/09 → 02/2/09

Keywords

Flexible electronics
Hybrid CMOS
NAND gate
NOR gate

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/FEDC.2009.5069280

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title = "Low temperature integration of hybrid CMOS devices on plastic substrates",

abstract = "The development of flexible Complimentary Metal-Oxide-Semiconductor (CMOS) circuits reduces power consumption by ∼50x compared to n-type (or p-type) only thin film transistor (TFT) digital circuits. In this work we demonstrate a new integration approach to fabricate CMOS circuits on plastic substrates (Poly-ethylene naphthalene, PEN). We use pentacene and amorphous silicon (a-Si:H) thin film transistors for p-type and n-type devices, respectively. The maximum processing temperature for n-type TFTs is 180°C and 120°C for the p-type TFTs. CMOS circuits demonstrated include inverters, NAND and NOR gates. nMOS and pMOS carrier mobility achieved after the CMOS integration process flow are 1.0 and 0.05 cm2/V-s, respectively. Threshold voltages (Vt) are 3.89V for nMOS and -1.89V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates are reported.",

keywords = "Flexible electronics, Hybrid CMOS, NAND gate, NOR gate",

author = "S. Gowrisanker and Quevedo-Lopez, {M. A.} and Alshareef, {H. N.} and B. Gnade and S. Venugopal and R. Krishna and K. Kaftanoglu and D. Allee",

year = "2009",

doi = "10.1109/FEDC.2009.5069280",

language = "English (US)",

note = "Flexible Electronics and Displays Conference and Exhibition, FLEX 2009 ; Conference date: 02-02-2009 Through 02-02-2009",

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TY - CONF

T1 - Low temperature integration of hybrid CMOS devices on plastic substrates

AU - Gowrisanker, S.

AU - Quevedo-Lopez, M. A.

AU - Alshareef, H. N.

AU - Gnade, B.

AU - Venugopal, S.

AU - Krishna, R.

AU - Kaftanoglu, K.

AU - Allee, D.

PY - 2009

Y1 - 2009

N2 - The development of flexible Complimentary Metal-Oxide-Semiconductor (CMOS) circuits reduces power consumption by ∼50x compared to n-type (or p-type) only thin film transistor (TFT) digital circuits. In this work we demonstrate a new integration approach to fabricate CMOS circuits on plastic substrates (Poly-ethylene naphthalene, PEN). We use pentacene and amorphous silicon (a-Si:H) thin film transistors for p-type and n-type devices, respectively. The maximum processing temperature for n-type TFTs is 180°C and 120°C for the p-type TFTs. CMOS circuits demonstrated include inverters, NAND and NOR gates. nMOS and pMOS carrier mobility achieved after the CMOS integration process flow are 1.0 and 0.05 cm2/V-s, respectively. Threshold voltages (Vt) are 3.89V for nMOS and -1.89V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates are reported.

AB - The development of flexible Complimentary Metal-Oxide-Semiconductor (CMOS) circuits reduces power consumption by ∼50x compared to n-type (or p-type) only thin film transistor (TFT) digital circuits. In this work we demonstrate a new integration approach to fabricate CMOS circuits on plastic substrates (Poly-ethylene naphthalene, PEN). We use pentacene and amorphous silicon (a-Si:H) thin film transistors for p-type and n-type devices, respectively. The maximum processing temperature for n-type TFTs is 180°C and 120°C for the p-type TFTs. CMOS circuits demonstrated include inverters, NAND and NOR gates. nMOS and pMOS carrier mobility achieved after the CMOS integration process flow are 1.0 and 0.05 cm2/V-s, respectively. Threshold voltages (Vt) are 3.89V for nMOS and -1.89V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates are reported.

KW - Flexible electronics

KW - Hybrid CMOS

KW - NAND gate

KW - NOR gate

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U2 - 10.1109/FEDC.2009.5069280

DO - 10.1109/FEDC.2009.5069280

M3 - Paper

AN - SCOPUS:70349902975

T2 - Flexible Electronics and Displays Conference and Exhibition, FLEX 2009

Y2 - 2 February 2009 through 2 February 2009

ER -

Low temperature integration of hybrid CMOS devices on plastic substrates

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Keywords

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