Low-Power Hardware Implementation of a Support Vector Machine Training and Classification for Neural Seizure Detection

Heba Elhosary, Michael H. Zakhari, Mohamed A. ElGammal, Mohamed Abd Elghany, Khaled N. Salama, Hassan Mostafa

Research output: Contribution to journalArticlepeer-review

29 Scopus citations


In this paper, a low power support vector machine (SVM) training, feature extraction, and classification algorithm are hardware implemented in a neural seizure detection application. The training algorithm used is the sequential minimal optimization (SMO) algorithm. The system is implemented on different platforms: such as field programmable gate array (FPGA), Xilinx Virtex-7 and application specific integrated circuit (ASIC) using hardware-calibrated UMC 65nm CMOS technology. The implemented training hardware is introduced as an accelerator intellectual property (IP), especially in the case of large number of training sets, such as neural seizure detection. Feature extraction and classification blocks are implemented to achieve the best trade-off between sensitivity and power consumption. The proposed seizure detection system achieves a sensitivity around 96.77% when tested with the implemented linear kernel classifier. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is improved by a factor of 2X when compared with the FPGA counterpart.
Original languageEnglish (US)
Pages (from-to)1324-1337
Number of pages14
JournalIEEE Transactions on Biomedical Circuits and Systems
Issue number6
StatePublished - Oct 14 2019

Bibliographical note

KAUST Repository Item: Exported on 2020-10-01
Acknowledgements: This work was partially funded by ONE Lab at Zewail City of Science and Technology and at Cairo University, NTRA, ITIDA, and ASRT.


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