Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance

Computer Science

• Machine Learning 100%
• Machine Learning Approach 100%
• Artificial Neural Networks 100%
• Timing Analysis 100%
• Iterative Algorithm 100%
• Feature Extraction 100%
• Interdependency 100%
• Memory Footprint 100%

Engineering

• Source Model 100%
• Current Source 100%
• Interconnects 100%
• SPICE 50%
• Iterative Algorithm 25%
• Feature Extraction 25%
• Interdependency 25%
• Learning Approach 25%
• Initial Stage 25%
• Resistive 25%
• Efficient Model 25%
• VLSI Circuits 25%
• Memory Footprint 25%
• Artificial Neural Network 25%

Keyphrases

• Current Source Model 100%
• Incremental Optimization 33%
• Initial Delay 33%
• Timing-driven 33%
• Timing Closure 33%
• Fast Iterative Algorithm 33%
• 7nm FinFET 33%